The invention relates to a circuit arrangement for recording the addresses of storage cells having erroneous contents with respect to coding and which are part of a memory configuration connected through a bus line system to a central control unit.
It is customary when processing data signals transmitted to a central control unit from peripheral equipment or from memory configurations, to check the data signals for error-free coding before they are processed. There are a great number of familiar coding processes for this purpose, which permit the recognition of specific errors in the data signals, caused by faults along the transmission path. When errors of this kind occur, it is desirable, for the systematic location of a faulty peripheral or memory configuration that is connected with the central control unit, to record addresses with regard to the peripheral or memory configuration emitting the erroneous data signals, for subsequent checking.